The present invention relates to a method for producing trench structures in silicon substrates for VSLI semiconductor circuits by reactive ion etching using an etching mask in a triode single-wafer plate reactor. The present invention also relates to the use of this method for producing trench structures.
European patent Application 0 338 207 discloses a method for etching trench structures in silicon substrates for semiconductor circuits. An atmosphere containing trifluorobromethane and nitrogen is used as an etching agent. A single-wafer plate reactor is provided that comprises a triode arrangement, whereby two different high-frequencies are beamed in. Such an arrangement is disclosed in European Patent Application 0 203 560.
In order to create integrated semiconductor memory circuits (DRAMs) having cell concepts beyond 4Mbit (16M, 64M), trench structures are required that, given a cross-sectional area of 1 .mu.m.sup.2 and a depth of at least 4 through 5 .mu.m, have profiles with vertical (through slightly slanting), smooth side walls and straight, flat trench floors (see the FIGURE) for the capacitors of the circuit. Attacks of the etching agent at the edges of the structure should be at a minimum, i.e., without "trenching." Microloading effects cannot be tolerated. In order to be able to achieve high electrical yields without having to implement additional after-treatment steps, damage to the substrate material must be as minimal as possible.